The present invention relates to the field of integrated circuits. More specifically, this invention relates to fashioning high-density micro electro-mechanical(MEM) structures.
Integrated circuits, at the die level, exhibit extremely high electronic circuit density. Electronic components, such as transistors, capacitors, and resistive elements are fabricated in integrated circuit dies at sub-micron level, and achieve densities on the order of millions of components per square inch and billions of components per cubic inch. However, this high density is easily forfeited as the dies are typically placed in packages, which contain bulky wires bonded to the enclosed die and connected to pins on the package. The package is predominately composed of empty space. FIG. 1 illustrates a typical integrated circuit 100 configuration, in which wires 115, 120, 125, etc., provide signal communication paths to and from integrated circuit die 110.
Packaged integrated circuits are further placed on a larger printed circuit board with most of the space occupied by pads that are used to connect the integrated circuits to the board. The packaged integrated circuits are further interconnected to achieve a desired functionality. As is known, the interconnections between integrated circuits introduce parasitic inductance and capacitance that effect the signals travelling between the integrated circuits. Accordingly, resistive, capacitive, and inductive devices are interposed in the interconnection paths to compensate for and reduce the level of introduced parasitic inductance and capacitance. FIG. 2 illustrates an exemplary printed circuit board (PCB) 200 containing a plurality of integrated circuits 210, 212, 218, 219, etc., coupling resistors 220, 222, etc., coupling capacitors 230, 232 etc., and coupling inductors 240, 242, etc.
Product package density is further reduced as multiple printed circuits boards are then electrically connected in racks, which, in turn, are housed in cabinets. Consequently, the resultant product density is considerably less than the achieved integrated circuit die density as the integrated circuit dies represent a negligible fraction of the overall product volume.
Thus, there is a need to develop structures of integrated circuit dies that achieve increased product packaging densities, reduce product dimensions and retain the benefits of high-density integrated circuit dies.
The present invention is associated with developing MEM component modules and using the MEM component modules to develop MEM structures that perform system level operations. MEM component modules are developed having a first surface and a second surface containing a plurality of via holes traversing the material from the first surface through to the second surface. The MEM component modules further include at least one integrated circuit die associated with said first surface and a cavity in the second surface in opposition to each of the at least one integrated circuit dies. The cavities are further sized substantially equal to a corresponding integrated circuit die. A MEM system level architecture comprises a plurality of MEM modules stacked vertically such that selective via holes in adjoining modules are in contact and provide at least one communication path between at least one first module and at least one vertically disposed module through via holes of intervening modules. Further, integrated circuit dies on one module are insertable into cavities of a module immediately disposed to provide a flush fit between stacked modules.